Accept Merge Request #898: (feature/制造代码优化 -> develop)

Merge Request: 修改zpl相关

Created By: @马广威
Accepted By: @马广威
URL: https://jikimo-hn.coding.net/p/jikimo_sfs/d/jikimo_sf/git/merge/898?initial=true
This commit is contained in:
马广威
2024-03-14 14:31:53 +08:00
committed by Coding
5 changed files with 20 additions and 7 deletions

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@@ -108,9 +108,9 @@ access_sf_production_line_group_plan_dispatch,sf.production.line,model_sf_produc
access_sf_production_line_group_plan_director,sf.production.line,model_sf_production_line,sf_base.group_plan_director,1,1,1,0
access_sf_production_line,sf.production.line,model_sf_production_line,sf_maintenance.sf_group_equipment_user,1,1,1,0
access_mrp_workcenter,mrp_workcenter,model_mrp_workcenter,sf_base.group_plan_dispatch,1,1,1,0
access_mrp_bom,mrp.bom,mrp.model_mrp_bom,sf_base.group_plan_dispatch,1,1,1,0
access_mrp_bom_group_plan_dispatch,mrp.bom,mrp.model_mrp_bom,sf_base.group_plan_dispatch,1,0,0,0
access_mrp_bom_line,mrp.bom.line,mrp.model_mrp_bom_line,sf_base.group_plan_dispatch,1,0,0,0
access_mrp_unbuild,mrp.unbuild,mrp.model_mrp_unbuild,sf_base.group_plan_dispatch,1,1,1,0
access_mrp_unbuild_group_plan_dispatch,mrp.unbuild,mrp.model_mrp_unbuild,sf_base.group_plan_dispatch,1,0,0,0
access_stock_scrap_group_plan_dispatch,stock.scrap,stock.model_stock_scrap,sf_base.group_plan_dispatch,1,0,0,0
access_sf_model_type,sf.model.type,model_sf_model_type,sf_base.group_plan_dispatch,1,1,1,0
1 id name model_id:id group_id:id perm_read perm_write perm_create perm_unlink
108 access_mrp_bom_line mrp.bom.line mrp.model_mrp_bom_line sf_base.group_plan_dispatch 1 0 0 0
109 access_mrp_unbuild access_mrp_unbuild_group_plan_dispatch mrp.unbuild mrp.model_mrp_unbuild sf_base.group_plan_dispatch 1 1 0 1 0 0
110 access_stock_scrap_group_plan_dispatch stock.scrap stock.model_stock_scrap sf_base.group_plan_dispatch 1 0 0 0
111 access_sf_model_type sf.model.type model_sf_model_type sf_base.group_plan_dispatch 1 1 1 0
112 access_mrp_routing_workcenter mrp.routing.workcenter mrp.model_mrp_routing_workcenter sf_base.group_plan_dispatch 1 1 1 0
113 access_mrp_document mrp.document mrp.model_mrp_document sf_base.group_plan_dispatch 1 0 0 0
114 access_sf_product_model_type_routing_sort sf.product.model.type.routing.sort model_sf_product_model_type_routing_sort sf_base.group_plan_dispatch 1 0 0 0
115 access_sf_embryo_model_type_routing_sort sf.embryo.model.type.routing.sort model_sf_embryo_model_type_routing_sort sf_base.group_plan_dispatch 1 0 0 0
116 access_sf_surface_technics_model_type_routing_sort sf.surface_technics.model.type.routing.sort model_sf_surface_technics_model_type_routing_sort sf_base.group_plan_dispatch 1 0 0 0

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@@ -19,7 +19,7 @@
],
'assets': {
'web.assets_backend': [
'jikimo_sfs/zpl_print/static/src/scss/changes.scss'
# 'jikimo_sfs/zpl_print/static/src/scss/changes.scss'
]
},
'license': 'LGPL-3',

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BIN
zpl_print/libs/TSCLIB11.dll Normal file

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@@ -8,14 +8,27 @@ class Common(models.Model):
_description = u'公用类'
def print_zpl(self, zpl_str):
WinDll_path = "D://桌面//pythonZPL//zebra_zpl//libs//TSCLIB.dll"
# WinDll_path = "D://桌面//pythonZPL//tsc_python_sdk_example//TSC_Python_SDK_Example//tsc_sample//libs//TSCLIB.dll"
WinDll_path = "D://jikimo-dev//jikimo//SF//zpl_print//libs//TSCLIB.dll"
# WinDll_path = "D://桌面//pythonZPL//zebra_zpl//libs//TSCLIB.dll"
try:
tsclibrary = ctypes.WinDLL(WinDll_path)
tsclibrary.openportW("USB")
print(type(zpl_str))
print(zpl_str)
tsclibrary.sendcommandW(zpl_str)
original_string = "^XA\n^FO100,50\n^A0N,44,33^FD[PO-2023-1226-0215-1] P-S00001-1^FS\n^FO100,100\n^A0N,44,33^FDLN/SN: P-S00001-1-12348啊a^FS\n^FO100,150^BY3\n^BCN,100,Y,N,N\n^FDP-S00001-1-12348啊a^FS\n^XZ"
# 使用加号操作符
new_string = original_string + "^CW1,E:SIMSUN.FNT #绑定字体\n^CI28 #UTF-8编码"
# 使用字符串格式化方法
new_string = "{}^CW1,E:SIMSUN.FNT #绑定字体\n^CI28 #UTF-8编码".format(original_string)
print(new_string)
tsclibrary.sendcommandW(new_string)
print('111222')
tsclibrary.printlabelW("0", "1");
tsclibrary.closeport();
tsclibrary.printlabelW("0", "1")
tsclibrary.closeport()
except Exception as e:
raise UserWarning("错误警告:%s" % e)